1 Introduction
    ICN6211 is a bridge chip which receives MIPI® DSI inputs and sends RGB outputs.
    MIPI® DSI supports up to 4 lanes and each lane operates at 1Gbps maximum; the totally maximum input bandwidth is 4Gbps; and the MIPI defined ULPS(ultra-low-power state) is also supported. ICN6211 decodes MIPI® DSI 16bpp RGB565 and 18bpp RGB666 and 24bpp RGB888 packets.
    The RGB output 18 or 24 bits pixel with pixel clock range of 25MHz to 154MHz.
    ICN6211 support video resolution up to FHD (1920x1080) and WUXGA(1920x1200).
    ICN6211 adopts QFN48 pins package.
1.1 Feature List
 Supports MIPI® D-PHY Version 1.00.00 and MIPI® DSI Version 1.02.00.
 Single Channel DSI Receiver with One, Two, Three and Four lanes configurable, each lanes operates up to 1Gbps.
 Receives 16bpp RGB565 and 18bpp RGB666 and 24bpp RGB888 packets defined by DSI.
 Supports MIPI Low State, Ultra-Low Power State, Shut Down mode.
 Output RGB with pixel clock range of 25MHz to 154MHz.
 RGB output supports flexible swap.
 Can adjust RGB Clock output phase(with 1/4, 1/2, 3/4 and fine adjust option) .
 Provides FRC/Hi-FRC function to improve 18bpp image performance.
 power supply : 1.8V/2.5V/3.3V for RGB output; 1.8V/2.5V/3.3V for MIPI and digital IO.
 provide I2C slave interface.

 package: QFN48-pins with e-pad.

2 Functional Block Diagram
Following figure shows a functional block diagram of the ICN6211.

3 System Application Diagram
In the diagram below shows the ICN6211’s system application.

4 Pin Diagram

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